Generating bit-streams with higher compression gains

ABSTRACT

A system ( 10 ) and method that generate bit-streams that result in higher compression gains. The system is akin to a normal 1-bit SDM. Internally, the system ( 10 ) tries to find the best possible bit sequence by tracing N possible solutions at every time instant. In an implementation, the system has N&gt;I trellis path structures ( 20 ). Every path is used to track a possible output bitstream. The quality of a bitstream is determined by measuring the (frequency weighted) difference between input and output; it is this measure that is reduced or minimized.

The present invention relates generally to a system and method forgenerating bit-streams and more specifically, to a system and method forgenerating bit-streams with higher compression gains.

Super-Audio Compact Discs (SACDs) use the Direct Stream Digital (DSD)format to store music. This 1-bit data format can be losslesslycompressed in order to increase playback time. Since the compression islossless, the compression gain is signal dependent. Different SigmaDelta Modulator (SDM) designs generate different bit-streams, whilehaving the same or comparable signal and noise transfer function (equalSNR, distortion, etc.). However, some SDM designs generate bit-streamsthat result in better compression, while other designs result in lesscompression. Current SDM designs cannot be tuned to deliver morecompression gain without signal degradation.

In order to fit 74 minutes of both stereo and multi-channel content on adisc, an average compression gain of 2.7 is required. Because of thesignal dependent coding gain, this compression gain is not achievablefor all material, not even with the best SDM designs. Pop-music, onwhich a lot of processing is performed, is problematic and in general,results in a low average compression gain. However, pop-music releasesare especially important for the SACD format to become a commercialsuccess.

Recently, several alternatives to the standard 1-bit Sigma DeltaModulator (SDM) have been proposed. These include tree-based, look-aheadsigma delta modulation, time-quantized frequency modulation, and trellisnoise-shaping conversion.

FIG. 1 shows the structure of a conventional SDM. In FIG. 1, x(t)represents the input signal, d(t) the error signal, c(t) the frequencyweighted error signal, and y(t) the output signal. The filter H(z)represents the frequency weighting (i.e., noise-shaping) function, whichis typically a low-pass function for an audio converter. Explicitlyshown in FIG. 1 is the delay z⁻¹ between the output y(t) and a feedbacksignal. As a result of this delay z⁻¹, the output at t=t_(O) isdetermined by the input signal x(t) up to t=t_(O), but also by thefeedback signal up to t=t_(O)−1. The feedback signal is thus in effect aprediction of the future. A correct prediction will generate a feedbacksignal that results in a small (instantaneous) frequency weighted errorsignal c(t). A bad prediction will increase the frequency weighted errorsignal c(t). Since the input signal x(t) is changing relatively slowlycompared to the sample rate, most predictions are correct and theconventional SDM is in stable operation. However, since the input x(t)is not known a-priori, the generated output (the feedback signal) willnot always be the ‘best possible’ output. An extreme example of theeffect of making incorrect predictions is when an SDM runs unstable andstarts to oscillate. The SDM will still try to minimize theinstantaneous error, but the total frequency weighted error signal c(t)will be large.

If the complete input sequence to the SDM x(t=0) . . . x(t=N) was known,one could, in theory, construct an output sequence y(t=0) . . . y(t=N)that would minimize the global frequency weighted error $\begin{matrix}{C = {\sum\limits_{t = 0}^{t = N}\left\lbrack {c(t)} \right\rbrack^{2}}} & (1)\end{matrix}$

However, for an input sequence with length N, the number ofpossibilities for the output sequence would be 2^(N), which can ingeneral be approximated by infinity. Therefore, searching for anapproximation of this optimal solution is necessary. This is thefunction of ‘full trellis’ noise-shaping algorithms.

For full trellis noise-shaping, it is assumed that up to t=t_(O), theoptimal output sequence is known. The output y(t=t_(O) +1) can be either−1 or +1, which will result in the instantaneous frequency weightederror c₀(t=t_(O)+1) and c₁ (t=t_(O)+1), respectively. One time instantlater, again an output of either −1 or +1 is possible, resulting in fourdifferent possibilities (paths) for the two output bits. Every path hasits own associated cost (called a pathmetric), defined as the sum of thesquared frequency weighted error values: $\begin{matrix}{{C_{W_{N}}(t)} = {\sum\limits_{t = 0}^{t}\left\lbrack {c(\tau)} \right\rbrack^{2}}} & (2)\end{matrix}$where

w_(N) is a sequence of N output bits.

Advancing time once more, the number of possibilities doubles again andbecomes eight, and so on. The full trellis algorithm limits the numberof paths by selecting, and continuing with, only half of the newlygenerated paths. In a full trellis system of order N, 2^(N) possiblesolutions are investigated at every moment in time. Advancing time by 1results in 2^((N+1)) candidates, of which 2^(N) are selected. The 2^(N)solutions under investigation are forced to be all different in thenewest N bits, in order to maintain the trellis structure.

FIG. 2 illustrates a conventional trellis with order N=2. FIG. 2illustrates the four combinations of two bits that are possible for timet−1. FIG. 2 illustrates the origination of new candidates (time t) fromold candidates (time t−1). A complete state diagram for 2^(N)=4candidates is shown on the left and the general case is shown on theright. For clarity, the signal level −1 is represented by the symbol “0”in FIG. 2.

If to the sequence ‘00’ a ‘0’ is concatenated, ‘000’ is obtained. Addinga ‘1’ results in ‘001’. Reducing the length of the two possiblesequences to two again, results in ‘00’ and ‘01’, respectively. It isclear that starting with ‘10’ would also result in ‘00’ and ‘01’,therefore a choice has to be made and one path has to be selected. Theselection criteria may be the total cost of the path; it is assumed thatthe path with the lower cost will turn out to be the best solution ofthe two. If

-   σ∈{−1, 1}, single output bit-   C_(w) _(N) ₉₄ (t) is the filter output after processing of σ when-   candidate W_(N) at t−1 is used.    the cost for the two candidates can be written as    c _(path 1) =C _(0w) _(N−1) (t−1)+[C _(0w) _(N−1) ^(σ)(t)]²    c _(path 2) =C _(1w) _(N−1) (t−1)+[C _(1w) _(N−1) ^(σ)(t)]²  (3)    and the new cost for the path is given by: $\begin{matrix}    {{C_{W_{N - 1^{\sigma}}}(t)} = \left\{ \frac{{C_{{path}\quad 1}\quad{if}\quad C_{{path}\quad 1}} \leq C_{{path}\quad 2}}{{C_{{path}\quad 2}\quad{if}\quad C_{{path}\quad 1}} > C_{{path}\quad 2}} \right.} & (4)    \end{matrix}$

The output of a system of order N, includes 2^(N) parallel bits. Theseoutput bits will in general not be the same, although the trellisalgorithm may presume them to be equal. If the system runs long enough,paths converge. This means, that independently of which path isexamined, they indicate the same output bit for t→−∞. FIG. 3 illustratesthe convergence. FIG. 3 illustrates the origination of the fourcandidates. The different candidates terminate with different outputsymbols, but in history (t→−∞) the output sequences converge to a singlesolution.

In practice, it is not necessary to trace back to t→−∞ in order tounambiguously determine the output of the system. An output latency upto several thousand bits, depending on the trellis order, is usuallyenough. Every path of the trellis converter has its own output history,all with equal length. One can view the history buffer as a shiftregister; the newly determined output bit is shifted in, and the latencyor history length time steps ago determined output shifts out. In normalsituations, all 2_(N) output bits will be equal, and the output isuniquely determined. However, when the history length is not longenough, the different paths might produce different output bits and theoutput cannot be determined unambiguously. This will result in so-calledtruncation noise.

Application of a trellis converter increases stability and improves SNR.Simulations have shown, that in order to significantly gain performance,the trellis order needs to be large. Since the workload doubles forevery increment of the trellis order, orders higher than 5 or 6 canhardly be used (a 6th order system contains 2⁶=64 SDMs, together withbookkeeping overhead, results in an about 100 times more expensivesystem than a normal SDM). Efficient trellis SDMs are known, which makeit possible to reach the performance of a 10th order full trellisconverter at the cost of only a 5th order system.

For efficient trellis noise-shaping, it is possible to increase thecomputational efficiency of the trellis converter by calculating afraction of the 2^(N) paths, denoted by M. These M paths are processedas if they are part of a normal trellis of order N.

However, there are still performance gains, for example, in terms ofrequired CPU power, stability and linearity compared to a conventionaltrellis SDMs.

An object of the invention is to refine the concept of efficient trellisnoise-shaping and/or introduces a system and method (which may beimplemented as an algorithm) that offers much better performance interms of required CPU power, stability, and/or linearity compared toconventional trellis SDMs.

To this end, a new SDM type is presented that generates bit-streamswhich result in higher compression gains. A trade-off between requiredCPU time and resulting compression gain can be made.

In one or more exemplary embodiments, the system includes Nweighting-filter devices (where N≧2), each receiving an input signal anda M-value feedback signal (where M≧2) and each generating M filteredoutput signals, a path sorter for applying at least one cost function tothe N*M filtered output signals to produce the N cheapest paths, anormalizer for normalizing the N cheapest paths, and an output devicefor selecting an output signal and for supplying the N M-value feedbacksignals to the N weighting-filters.

In one or more exemplary embodiments, the at least one cost function isa function of at least one output signal characteristic.

In one or more exemplary embodiments, each of the N weighting-filterdevices includes a M-value generator and a filter.

In one or more exemplary embodiments, each weighting-filter deviceincludes a subtractor for subtracting the input signal and the M-valuefeedback signal and filtering the M output signals.

In one or more exemplary embodiments, the M-value feedback signalincludes two values, −1 and 1.

In one or more exemplary embodiments, N is fixed or adaptive. In one ormore exemplary embodiments, each of the weighting-filter devicesincludes a fixed order, fixed frequency response filter; a fixed order,variable frequency response filter; a variable order, fixed frequencyresponse filter; a variable order, variable frequency response filter;or a noise-shaping filter adjustable for Direct Stream Transfer (DST)performance.

In one or more exemplary embodiments, the system is implemented insoftware and/or hardware.

In one or more exemplary embodiments, the system is used foranalog-digital, digital-analog, and/or digital-digital (AD/DA/DD)conversion and/or pulse width modulation (PWM).

In one or more exemplary embodiments, the method includes receiving aninput signal and at least two M-value feedback signals (where M≧2) andgenerating M*N filtered output signals, applying at least one costfunction to the M*N filtered output signals to produce the N cheapestpaths, normalizing the N cheapest paths, and selecting an output signalfrom the N cheapest paths and for generating the at least two M-valuefeedback signals.

In contrast to the original efficient trellis algorithm, the concept oftrellis order is not used. Complexity is determined by the number ofpaths to process, called trellis depth N. A trellis path structure mayinclude a history buffer with fixed length, path-cost variable, and atrellis SDM integrator state memory.

To this end, a new method (for M=2) is presented, where:

-   1. For all N paths, the total path cost for the two output bits is    determined.-   2. The 2N solutions are sorted on total path cost.-   3. The N cheapest paths are selected and processing continues.-   4. The path costs are normalized.-   5. The output bit corresponding to history-length inputs ago is    determined.-   6. Paths that do not converge are invalidated.

Step 1 may use any cost function or functions. In step 2 in combinationwith step 3, the number of solutions is halved, in order to keep N pathsinstead of doubling the number of solutions every time instant. Theassumption made is that the cheaper the path, the larger the probabilityof it being the optimal path. In order to overcome the problem ofconstantly increasing path cost values, in step 4 the path costs may benormalized, with the cheapest path getting a score of 0, for example. Instep 5, the output is determined. This output bit corresponds to theinput sample history-length inputs ago. This input-output delay keepsthe system causal. Ideally all N paths dictate the same output bit.However, if the history length is not long enough, convergence on thesolution has possibly not been reached yet within history-length timesteps. If this happens, solutions that are not in agreement with theoutput (which is based on the best (cheapest) path) can be rejected.

Correct initialization is useful, since N parallel identical SDMs willgenerate the same output if initialized identical. An exemplary solutionis to initialize one path structure to 0 cost, and all the others to alarge cost. The expensive paths will die out in log₂(N) clock cycles andthe system will be fully functional, tracing N different paths. As setforth above, in other exemplary embodiments, M may be any value ≧2.

The present invention will become more fully understood from thedetailed description given below and the accompanying drawings, whichare given for purposes of illustration only, and thus do not limit theinvention.

FIG. 1 shows the structure of a conventional SDM.

FIG. 2 illustrates a conventional trellis with order N=2.

FIG. 3 illustrates the origination of the four candidates and pathconvergence.

FIG. 4 illustrates a system in accordance with an exemplary embodimentof the present invention.

FIG. 5 illustrates a weighting-filter device 20 of FIG. 4, in accordancewith an exemplary embodiment of the present invention.

FIG. 6 illustrates the operations of the system of FIG. 4, in accordancewith an exemplary embodiment of the present invention.

FIG. 7 illustrates the different paths under investigation, inaccordance with an exemplary embodiment of the present invention.

FIG. 8 shows the relationship between the number of trellis paths andrequired CPU time, in accordance with an exemplary embodiment of thepresent invention.

FIG. 9 shows the relationship between the number of trellis paths andoutput signal quality, in accordance with an exemplary embodiment of thepresent invention.

FIG. 10 illustrates the maximum input amplitude that can be applied to asystem, in accordance with an exemplary embodiment of the presentinvention.

FIG. 11 illustrates the maximum noise-shaping filter comer frequencythat can be applied to a system, in accordance with an exemplaryembodiment of the present invention.

FIG. 4 illustrates a system 10 in accordance with an exemplaryembodiment of the present invention. The system 10 includes Nweighting-filter devices (N≧2)20_(t . . . N) which receive an inputsignal x(t) and output N×M paths, a path sorter 30 which sorts the N×Mpaths into the N cheapest paths, a normalizer 40, which normalizes the Ncheapest paths to the cheapest path, and an output device 50 whichoutputs the output y(t) and N feedback signals to the N weighting-filterdevices (N≧2)20_(t . . . N).

FIG. 4 illustrates three weighting-filter devices 20 (although thisnumber could vary). Each weighting-filter device 20 outputs C₊₁(t) andC⁻¹(t) and the path sorter 30 receives six values C(t) withcorresponding integrator states. The values C(t) are sorted in order tofind the three paths that have the lowest accumulated cost. The threecheapest paths are then passed to the normalizer 30, where the costvalue of the cheapest path is subtracted from all cost values. Thenormalizer 30 solves the problem of ever increasing values. In strictsense, there is no normalization performed, but only a new referencelevel set. The normalizer 30 could be implemented as one or moresubtractors.

In the output device 50, all output paths that are generated can bedifferent. however, going back in the past, the paths will most likelybe equal. The last bit in the history buffer of the cheapest pathdetermines the output. If the paths converge, all paths will have thislast bit equal. If the last bit of a path is different from the output,this path can be invalidated. A practical way of doing this is increasethe cost of this path by a large amount; the basic operation is thusperforming N—1 comparisons and possibly performing N−1 additions.

A generalized algorithm (for M=2, although as set forth above, M may beany value ≧2) representing exemplary embodiments of the presentinvention may be represented in pseudo-code by:

-   1. For all N paths determine the total path cost for the two output    bits.-   2 . Sort the 2N solutions on total path cost.-   3. Select and continue with the N cheapest paths.-   4. Normalize path cost.-   5. Determine the output bit corresponding to history-length inputs    ago.-   6. Invalidate paths that do not converge.

For every path, a weighting-filter device 20 is used. An exemplaryweighting-filter device 20 is shown in more detail in FIG. 5. Theweighting-filter device 20 receives the input signal x(t), loop filterstates S, and current cost C for each path. As shown in FIG. 5, there isno delay between the input x(t) and the output. The signal fb(t) is usedas a ‘feedback’ signal, and need not be generated by means of aquantizer but e.g. by a M-value generator. The value +1 and −1 areapplied as signal fb(t). Two outputs are generated and passed on to thepath sorter 30.

To determine the output, one or more history buffers may be used. Ahistory buffer is a memory, that remembers the past outputs generated bya weighting-filter device 20. The history buffer(s) can unambiguouslydetermine the output of the system 10; if going back far enough in time,the N paths are all equal. An integrator state memory may also be usedfor setting and restoring the filter H(z). Applying an input to thefilter H(z) changes the integrator states. Since both +1 and −1 can beapplied, in between the original integrator states need to be restored.Every path that is traced, has it's own integrator states; the paths aredifferent and thus also the integrator states.

Output include the new path cost, updated history buffer, and updatedstate variables for both the −1 path and the +1 path. The total pathcost for the 0 (−1) branch and 1 (+1) branch, respectively, is given by:c ₀(t)=C _(W)(t−1)+[C _(W0)(t)]²c ₁(t) =C_(W)(t−1)+[C _(W1)(t)]²   (5)

The path cost thus reflects the frequency weighted error of the completepath starting at t=0. In order to overcome the problem of constantlygrowing path cost values, the path cost can normalized after every timestep, with the cheapest path having a cost of 0.

FIG. 6 schematically shows a system 10 with N=2 calculating its outputover four time steps. The resulting bit-streams are shown. The twobit-streams that are kept at each time step have a box drawn aroundthem. The bit-streams without a box will not continue to the next timestep. The italic numbers next to the branch lines indicate thenormalized path cost for the branch.

At time t, there is a bit-stream ‘0’ and ‘1’. Concatenating a ‘0’ and‘1’ to both bit-streams will give the four possible solutions for timet+1. For both paths, the ‘0’ branch results in the cheapest path,resulting in bit-streams ‘00’ and ‘10’ for time t+1. Concatenation of‘0’ and ‘1’ results in the four new candidate solutions for time t+2.The total path cost for both paths originating from ‘00’ is lower thanthe cost for the paths originating from ‘10’, which is not continued.The path ‘00’ is duplicated and extended to ‘000’ and ‘001’. Note thatthe path that is cheapest at time t+2 will not continue to time t+3; alocal minimum will not necessarily result in a global minimum.

It is assumed all N weighting-filter device 20 are initialized the same(e.g. path cost =0, integrator states all 0, and path history bufferfilled with digital silence). At startup, all N weighting-filter device20 will calculate the same instantaneous cost for the first output bit(N times the same cost for the −1 output, N times the same cost for the+1 output). Since the path cost is initialized the same for all paths,the total path cost will be the same. Thus, the selection of the Ncheapest paths out of the 2N possibilities will result in N paths thatare equal, and the performance of the system 10 will be equal to that ofone path. By initializing the path cost of one path to 0, and to a largevalue for the other paths, the system 10 can reject all expensive pathsand continue with the solutions of the initial cheap path and itsbranches. After log₂(N) clock cycles, the system 10 will be fullyoperational and have N different paths. Because the integrator states ofevery path's weighting-filter device 20 are unique, the weighting-filterdevice 20 output bits will not become equal and there is no need tocheck and enforce differentiation of the paths.

Just as in a conventional SDM, a system 10 generates an output sampleevery clock cycle. However, the most recent output sample was generatedin response to input samples history-length clock ticks ago. Since everynew input sample can, in theory, cause the system 10 to branch all itspaths, and reject half of its solutions, convergence of all paths can bealmost instantaneous. However, it is also possible that all N solutionsare reasonable and continued to the next time step. In practice, bothsituations are not very common and only a few long unique paths aretracked. The ‘heads’ of the paths contain a lot of small ‘fingers’, thattry all possibilities for the newest bits. FIG. 7 illustrates thesefingers. The thicker lines correspond to paths that are equal.

Selection of what bit to output is straight-forward, it is the oldestbit in the history buffer of the cheapest path. To avoid introducing anyclicks in the output bit-stream, paths that are not in accordance withthe output, can be eliminated. The selection of the output bit, is incontrast to the original trellis algorithm, unambiguous and independentof convergence. Truncation noise will not be generated.

Because of the latency introduced by the history buffer, at startup, thesystem 10 will first output data that is not correlated to the inputsignal. Only after history length input samples, will actual data becoming out of the system 10. The inverse problem exists at the end ofinput. Appending additional input silence can be used to flush thebuffers.

As shown in FIG. 5, one or more cost functions can be used to generateC₊₁(t) and C⁻¹(t). An example of a cost function C is given by$\begin{matrix}{C_{1} = {\sum\limits_{t = 0}^{t}\left\lbrack {c(t)} \right\rbrack^{2}}} & (6)\end{matrix}$in order to determine the quality of the output bit-streams. Other costfunction examples include: $\begin{matrix}{{C_{2} = {\sum\limits_{t = 0}^{t = N}{{c(t)}}}}{or}} & (7) \\{C_{3} = {\sum\limits_{t = 0}^{t = N}{\alpha \cdot \left\lbrack {c(t)} \right\rbrack^{2}}}} & (8)\end{matrix}$or more generally: $\begin{matrix}{C_{4} = {\sum\limits_{t = 0}^{t = N}{F\left( {t,{x(t)},{y(t)},{c(t)}} \right)}}} & (9)\end{matrix}$where F ( ) takes as inputs, time, the input value, the output value,and the output value, and performs any function on these.

In another exemplary embodiment, the number of paths varies adaptively.Depending on the quality of the generated bit-streams, more or fewerpaths can be calculated. This can be e.g. used to achieve higherperformance, or reduce computational load. TABLE 1 Average compressiongain as function of the number of paths. Paths avg. compression SDM 2.671 2.67 4 2.98 8 3.07 16  3.13 32  3.17

Table 1 shows the obtained average DST compression gain listed asfunction of the number of paths. For the data in Table 1, the inputsignal is a 1 kHz sine wave, amplitude 0.5. The loop filter used isdesigned to have a Butterworth characteristic with 105 kHz comerfrequency, with resonators at 15 and 19 kHz added. The unweighedmeasured SNR of this design is 121 dB for the given sine. The bitstreamof a normal SDM with the same SNR results in a compression of 2.67.

Exemplary embodiments of the present invention may be used in thecreation of 1-bit content for Super Audio CD (SACD). Exemplaryembodiments of the present invention may be implementation in hardwareor software as would be know to one of ordinary skill in the art.

Exemplary embodiments of the present invention may require a historylength of around 500 samples for a one to four path system, and around3000 samples for 32 paths. This should not present a memory size forcopying such amounts of memory for every path. When circular buffers areused, most of this copying is not necessary. However, since paths splitup quite often, not all copying can be avoided. The same holds for theweighting-filter device states, when a path splits up in two paths, theintegrator states may be duplicated, as well as the path cost.

Sorting of the 2N paths on cost should be implemented with care. Sincethe number of elements to sort is small, generally fast sorts likequicksort or flashsort may perform poorly. A basic insertion sort showsgood performance, since the list is in nearly sorted order. Use of anadditional pivot as first element can speed up the inner loopsignificantly.

FIG. 8 shows the relation between the number of trellis paths andrequired CPU time. Three different data sets have been used as testsignals. The main part of the method is linear in the number of trellispaths. The sorting on cost of the paths adds on average O(nlog(n))behavior (best case linear, worst case n²). The total method istherefore almost linear. The three different data sets show nodifference in processing time. Different settings of history length havealso hardly any influence on execution speed (maximum few percent) andis therefore not shown.

Performing a fair comparison between a weighting filter device and anormal SDM is not so easy. The Noise Transfer Function (NTF) of a normalSDM is given by $\begin{matrix}{{NTF}_{SDM} = \frac{1}{1 + {H(z)}}} & (10)\end{matrix}$whereas the NTF of a weighting filter device is given by $\begin{matrix}{{NTF}_{TrellisSDM} = \frac{1}{H(z)}} & (11)\end{matrix}$

If the same loop filter is used, the SNR of the normal SDM will behigher since it suppresses the noise more. However, an equivalent loopfilter for a weighting filter device can be designed, which will resultin the same NTF for a converter with one Trellis path. A comparison ofthe same trellis converter with a different number of paths is thereforemore interesting.

FIG. 9 shows a zoom-in of the output spectra for a 0 dB SACD 1 kHz inputfor 8, 16, and 32 Trellis paths (5th order loop filter, 2.8 MHz samplerate, corner frequency 105 kHz, notches at 15 and 20 kHz). The spectrahave been coherently power averaged 128 times in order to make allharmonic distortion visible and 64 times power averaged for smoothplots. Clearly visible is the strong decrease in coherent power forincreasing number of trellis paths, indicating increasing linearity. Thesystem 10 with 32 paths does not show any harmonic distortion, not evenafter the 128 coherent averages. As a reference, the 64 times poweraveraged spectrum for a normal undithered SDM is shown. All harmonicpower of the system 10 solutions is below the noise level of a normalSDM, even without the use of dither.

FIG. 10 illustrates the maximum input amplitude that can be applied toan exemplary system 10 (5^(th) order, sample-rate 2.8 Mhz, cornerfrequency 105 kHz, notches at 15 and 20 kHz) that still results instable operation. The test tone is a 1 kHz sine wave. Going from 1 to128 paths results in an increase of maximum input amplitude of more than30%. Going to 8 paths increases the maximum input amplitude from 0.66 to0.81, an increase of almost 23% already.

The increase in stability can also be used to perform more aggressivenoise-shaping. To create FIG. 11, the input has been kept constant at 0dB SACD while the maximum stable corner frequency of the loop filter isexamined as function of the number of trellis paths. Again the 5^(th)order loop filter contains two notches at 15 and 20 kHz. For one trellispath, the maximum corner frequency that results in stable operation is137 kHz. Going to 8 paths increases this limit to 217 kHz, while 128paths results in a maximum stable corner frequency of 445 kHz.

It is further noted that the input need not be restricted to abitstream; the input may be analog or digital. It should be noted thatthe above-mentioned embodiments illustrate rather than limit theinvention, and that those skilled in the art will be able to design manyalternative embodiments without departing from the scope of the appendedclaims. In the claims, any reference signs placed between parenthesesshall not be construed. as limiting the claims. The word “comprising”does not exclude the presence of other elements or steps than thoselisted in a claim. The modifiers “a”, “an”, “one” and “at least one” asused in the appended claims all are intended to include one or more ofwhatever they modify. The invention can be implemented by means ofhardware comprising several distinct elements, and by means of asuitable programmed computer. In a device claim enumerating severalmeans, several of these means can be embodied by one and the same itemof hardware. The mere factor that certain measures are recited inmutually different dependent claims does not indicate that a combinationof these measures cannot be used to advantage.

1. A system (10), comprising: N weighting-filter devices (where N≧2) (20), each receiving an input signal and a M-value feedback signal (where M≧2) and each generating M filtered output signals; a path sorter (30) for applying at least one cost function to the N*M filtered output signals to produce the N cheapest paths; a normalizer (40) for normalizing the N cheapest paths; and an output device (50) for selecting an output signal and for supplying the N M-value feedback signals to the N weighting-filters (20).
 2. The system (10) of claim 1, wherein the at least one cost function is a function of at least one output signal characteristic.
 3. The system (10) of claim 1, wherein each of the N weighting-filter devices (20) includes a M-value generator and a filter.
 4. The system (10) of claim 3, wherein each weighting-filter device (20) includes a subtractor for subtracting the input signal and the M-value feedback signal and filtering the M output signals.
 5. The system (10) of claim 1, wherein the M-value feedback signal includes two values, −1 and
 1. 6. The system (10) of claim 1, wherein N is fixed or adaptive.
 7. The system (10) of claim 4, wherein each of the weighting-filter devices (20) includes a fixed order, fixed frequency response filter; a fixed order, variable frequency response filter; a variable order, fixed frequency response filter; a variable order, variable frequency response filter; or a noise-shaping filter adjustable for Direct Stream Transfer (DST) performance.
 8. The system (10) of claim 1, wherein the system (10) is implemented in software and/or hardware.
 9. The system (10) of claim 1, wherein the system (10) is used for analog-digital, digital-analog, and/or digital-digital (AD/DA/DD) conversion and/or pulse width modulation (PWM).
 10. A method, comprising: receiving an input signal and at least two M-value feedback signals (where M≧2) and generating M*N filtered output signals; applying at least one cost function to the M*N filtered output signals to produce the N cheapest paths; normalizing the N cheapest paths; and selecting an output signal from the N cheapest paths and for generating the at least two M-value feedback signals. 